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High Performance Gigabit Ethernet MAC

IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Communication and Networking
IP Supported FPGA Device: 
Cyclone
Cyclone II
Stratix
Stratix II
IP Description: 

The High Performance Gigabit Ethernet MAC includes the following features:

Up to 114 Mbytes of UDP data
1000 Base-T, full duplex
100 Base-TX, full duplex
Transmit buffer: double buffer, 2000 bytes, checksum advance logic
Receive buffer: ring buffer, 4000 bytes
Filter: MAC ID, MAC IP
Integrated DMA controller: pipelined, generates checksum on the fly, alignment aware
IFI_PHY_MANAGER included
Nios® II embedded processor interface

Description
Easily integrated into Nios II systems using SOPC Builder
Avalon® interface for Nios II processor
Independent clock domains for Nios II and GMAC II
Royalty free
Ethernet and Gigabit Ethernet PHY module available
Verified on Nios II development board
Evaluation version available

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