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Power Implications of Implementing Logic Using FPGA Embedded Memory Blocks
September 10, 2008 - 4:03pm — scottcOn-chip user memory has become a common resource on modern FPGAs. This memory comes in the form of configurable Embedded Memory Blocks (EMB). EMBs are very area efficient for implementing designs
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HDLC, Single-Channel
May 29, 2007 - 2:08pm — fc
IP Vendor:
AvnetIP Type:
DesignIP Target Vendor:
XilinxIP Category:
Communication and NetworkingIP Supported FPGA Device :
Spartan-3
Virtex-II
Virtex-II Pro
IP Description:
"The Memec Design Single-Channel XF-HDLC Controller serves as a starting point for a custom design that gives full duplex operation, 16-bit/32-bit CCITT-CRC generation and checking. Features include flag and zero insertion and detection, DC to 53 Mbps (STS-1) data rate, full synchronous operation, and possible user customation of FIFO and DMA interfaces.
Device Family Support
Virtex-II Pro
Virtex-II
Spartan-3
Key Features
16/32-bit frame sequence
8/16-bit addr insert/delete, flag/zerop insert/detection"
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