What is your preferred platform for FPGA Design Flow ?:

H.264 / MPEG4 Part 10, Decoder, Baseline

IP Target Vendor: 
IP Type: 
IP Category: 
Audio, Video and Image Processing
IP Supported FPGA Device: 
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-II Pro
IP Description: 

"The H.264 / MPEG4 Part 10, Decoder, Baseline core is a fully pipelined dedicated video compression engine capable of supporting the H.264 / AVC / MPEG4 Part 10 video standard. The core reads an input bit stream (and reference pictures) from external memory and outputs a decoder picture back to memory. Host processor requirements are minimal and only a few registers specifying the active sequence and picture parameter sets must be programmed at boot up. The core itself may be either fully or partially autonomous. The core requires a single external memory component. This component may be any of SRAM, SDRAM or DDRAM types. The memory must be large enough to store the required number of reference frames. Typically 64 bit SDR or 32 bit DDR is adequate. The memory bus and core are fully asynchronous and the memory core transfers can be carried out at the highest achievable memory clock speed for maximum efficiency. The core can also generally share this memory with the host or render components with no loss of performance. Additionally, 4i2i can supply a range of video processing modules including video scaling, noise reduction and de-interlacing. A Xilinx FPGA based demonstration system can be provided for evaluation or development purposes.

Device Family Support
# Virtex-4 FX
# Virtex-4 LX
# Virtex-4 SX
# Virtex-II Pro
# Spartan-3L
# Spartan-3E
# Spartan-3

Key Features
# I and P slices.
# Quarter pixel interpolation.
# Multiple reference frames.
# Deblocking filter.
# Intra prediction for all 16x16 & 4x4 (luma) and 8x8 (chroma) modes.
# Inter prediction for all 16x16 down to 4x4 block sizes."

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