Poll

What is your preferred platform for FPGA Design Flow ?:

H.264 Encoder, Baseline

IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
Audio, Video and Image Processing
IP Supported FPGA Device: 
Spartan-3
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-II Pro
IP Description: 

"The AllianceCORE H.264 Encoder, Baseline from 4i2i is fully a pipelined dedicated video compression engine that implements the H.264 (baseline) encoding standard. The core reads a video frame from external memory and outputs an encoded bit stream (and decoded reference picture) back to memory. Host processor requirements are minimal and only a few registers (specifying the frame locations and coding options) need be programmed once at the beginning of each frame. The core requires single memory component, which may be any of SRAM, SDRAM or DDRAM. If the memory is fast enough then the core can generally share this memory with other encoder cores and the host and capture components with no loss of performance. Several encoder cores may also be composed into a single core, capable of seamlessly encoding video at HDTV rates even in the slowest FPGA families. The encoder cores are also configurable at build time, with both the number of reference frames, and number of motion estimators per reference frame being configurable. This allows higher performance implementations in larger components. At run time various rate distortion parameters including quantizer, intra and motion estimator biases are programmable on registers. This allows the encoder to be configured for optimal performance on the particular video data.

Device Family Support
# Virtex-4 FX
# Virtex-4 LX
# Virtex-4 SX
# Virtex-II Pro
# Spartan-3

Key Features
# Throughput:CIF: 352x288 x 30FPS @ 14 MHz
# PAL: 704x576x25 fps @ 56 MHz
# NTSC: 704x480x30 fps @ 56 MHz
# Max Single Core Frame Size:2048 x 2048
# Seamless Multi Core HDTV Encoding
# Reference Frames: 1 - 5
# Integer Pixel Search Range:Max +/-256 H x +/-256 V Local Searches"

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