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What is your preferred platform for FPGA Design Flow ?
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Total votes: 3278

Framer, STM0/OC1, STM1/OC3, STM4/OC12

IP Vendor: 
Aliathon
IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
Communication and Networking
IP Supported FPGA Device: 
Spartan-3
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-II
Virtex-II Pro
IP Description: 

"Aliathon's STM0/1/4 Framer core provides a flexible, resource-efficient solution for SDH interfacing. It caters for both concatenated payloads, such as VC4-4c over STM4, and channelised applications, such as multiple VC3s over STM1. The core may be connected to other Aliathon cores to implement complete SDH/PDH solutions.

Device Family Support

Virtex-4 FX

Virtex-4 LX

Virtex-4 SX

Virtex-II Pro

Virtex-II

Spartan-3

Key Features

Generates SDH frames for STM0, STM1 and STM4. The core may be dynamically switched between SDH rates.

Scrambles the SDH frame, inserts Regenerator Section Overhead, and calculates B1 values.

Inserts Multiplex Section Overhead and calculates B2 values.

Generates all AU pointers (up to 12 for VC3 over STM4).

Inserts VC3, VC4 and VC4-4c, both channelised and single-channel. All legal combinations of VCs are supported.

Generates B3 values for all VCs and inserts Higher Order Path Overhead."

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