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Forward Discrete Wavelet Transform (FDWT)

IP Vendor: 
IP Target Vendor: 
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IP Supported FPGA Device: 
Hardcopy Stratix
Stratix II
IP Description: 

Compliant with ISO/IEC 15444-1 Information Technology: JPEG2000 Image Coding System
2D decomposition with a programmable number of decomposition levels from 0 (bypass) up to five
Programmable lossless integer 5/3 or lossy floating point 9/7 filter
Periodic symmetric border extension (according to JPEG2000 standard)
Compact lifting scheme architecture with successive vertical and horizontal 1-D decompositions
16-bit data path; fixed-point 9/7 approximation
Fully configurable tile size, from 1 x 1 pixel up to 128 x 128 pixels; configurable tile offset
Internal tile buffer for increased performance
Configurable pixel depth and sign up to 16 bits (almost limited to 12 bits in lossless; 10 bits in lossy)
High-speed pixel interface, allowing transfer of 1 pixel per clock cycle on an entire tile
Easy slave pixel interface through simple synchronous protocol
Easy slave coefficient interface through direct read access to internal tile buffer (SRAM type) and simple addressing of resultant decomposed sub-bands in tile buffer
Availability of used decomposition parameters at the coefficient interface for easing integration in a compression chain
Efficient pipelined architecture
Fully synchronous design for easing integration with provided multi-cycle definitions for increasing performance
Single clock design

Figure 1 illustrates a simplified block diagram of the BA113FDWT intellectual property (IP), showing the internal modules and the interfaces. The BA113FDWT IP is a tile-level 2-D discrete wavelet transform (DTW) engine decomposing a rectangular tile of any size up to 128 by 128 pixels into multiple frequency sub-bands. The BA113FDWT pixel interface can accept an entire tile at high speed with no interruption.

The IP core handles up to five multiple decompositions internally. It stores the resultant decomposed subbands into its internal tile buffer where data can be fetched via the coefficient interface by simply addressing the tile buffer. Decomposed data is arranged in an easy way to facilitate subband access. Each sub-band is separately accessible from the tile buffer.

In addition, access to the coefficient interface allows the parameters to be used for decomposing the tile, which correspond to the parameters specified at the global configuration interface. This eases the integration of the wavelet core into a processing chain where decomposition parameters are needed by the next process. This feature allows the decomposition parameters to change for processing the next tile and keeps the further processes in tune with the actual parameters used for a given tile."

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