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Floating Point Square Root Operator

IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
Math
IP Supported FPGA Device: 
Spartan-3
Spartan-3E
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-II Pro
IP Description: 

"The AllianceCORE DFPSQRT uses the pipelined mathematics algorithm to compute square root function. The input number format is according to IEEE-754 standard. DFPSQRT supports single precision real numbers. SQRT operation can be pipelined up to 9 levels. Input data are fed every clock cycle. The first result appears after 9 clock periods latency and next results are available each clock cycle. Precision and accuracy are parameterized.

Device Family Support

Virtex-4 FX

Virtex-4 LX

Virtex-4 SX

Virtex-II Pro

Spartan-3L

Spartan-3E

Spartan-3

Key Features

Full IEEE-754 compliance.

Single precision real format numbers.

Simple interface.

Results available at every clock.

Overflow, underflow and invalid operation flags.

Fully configurable.

Fully synthesizable, static synchronous design with no internal tri-states."

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