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Floating Point Pipelined Multiplier Unit

IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Math
IP Supported FPGA Device: 
Stratix
Stratix II
IP Description: 

"Features
Fully complies with the IEEE 754 specification
Single-precision real format support
Simple interface
No programming required
Seven levels of pipelining
Full accuracy and precision
Overflow, underflow, and invalid operation flags
Results available at every clock
Fully configurable
Fully synthesizable, static synchronous design with no internal tri-states
Description
The DFPMUL floating-point pipelined multiplier unit function uses the pipelined mathematics algorithm to multiply two arguments. The input number format complies with the IEEE 754 specification, and the function supports single-precision real numbers. The multiply operation can be pipelined up to 7 levels. The input data are fed in every clock cycle. The latency before the first result appears depends on the level of pipelining; subsequent results are available at each clock cycle. The DFPMUL megafunction offers full accuracy and precision."

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