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Floating-Point Pipelined Divider Unit

IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Math
IP Supported FPGA Device: 
Stratix
Stratix II
Stratix II GX
Stratix III
IP Description: 

"Features
Fully complies with IEEE-754 specification
Single-precision real-format support
Simple interface
No programming required
Fifteen levels of pipelining
Fully accurate and precise
Results available at every clock
Overflow, underflow, and invalid operation flags
Fully configurable
Fully synthesizable, static-synchronous design with no internal tri-states
Description
The DFPDIV megafunction uses the pipelined mathematics algorithm to divide two arguments. The input number format complies with the IEEE 754 specification, and the function supports single-precision real numbers. The divide operation is pipelined to 15 levels, and the input data is fed in at every clock cycle. The first result appears after 15 clock periods of latency, and the subsequent results are available at each clock cycle."

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