Poll

What is your preferred platform for FPGA Design Flow ?
Windows
55%
Linux
36%
Solaris
1%
Mixed
2%
Other
1%
No preference
4%
Total votes: 4703

Floating Point Multiplier

IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
Math
IP Supported FPGA Device: 
Spartan-3
Spartan-3E
Spartan-IIE
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-II Pro
IP Description: 

"The AllianceCORE DFPMUL uses the pipelined mathematics algorithm to multiply two arguments. The input numbers format is according to IEEE-754 standard. DFPMUL supports single precision real number. Multiply operation was pipelined up to 7 levels. Input data are fed every clock cycle. The first result appears after latency depending on pipeline level and next results are available each clock cycle. Full IEEE-754 precision and accuracy were included.

Device Family Support

Virtex-4 FX

Virtex-4 LX

Virtex-4 SX

Virtex-II Pro

Spartan-3L

Spartan-3E

Spartan-3

Spartan-IIE

Key Features

Full IEEE-754 compliance

Single precision real format numbers

Simple interface

Results available at every clock

Overflow, underflow and invalid operation flags

Fully configurable

Fully synthesizable, static synchronous design with no internal tri-states"

Facebook  Twitter  Linkedin  YouTube      RSS

 

Check out FPGA related videos

Find Us On Facebook