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What is your preferred platform for FPGA Design Flow ?:

Floating-Point-to-Integer Pipelined Converter

IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Math
IP Supported FPGA Device: 
Cyclone
Stratix
Stratix II
Stratix II GX
Stratix III
IP Description: 

"Features
Full IEEE-754 compliance
Single-precision real input numbers
Double word output numbers (up to 4 bytes)
Simple interface
No programming required
Two levels of pipelining
Full accuracy and precision
Results available at every clock
Overflow, underflow, and invalid operation flags
Fully configurable
Fully synthesizable, static-synchronous design with no internal tri-states
Description
The DFP2INT megafunction supports single-precision real numbers and double-word integers up to 4 bytes. The convert operation is pipelined to two levels, and the input data is fed in at every clock cycle. The first result appears after two clock periods of latency, and the subsequent results are available at each clock cycle."

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