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What is your preferred platform for FPGA Design Flow ?:

Floating Point to Integer Converter

IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
Math
IP Supported FPGA Device: 
Spartan-3
Spartan-3E
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-II Pro
IP Description: 

"The AllianceCORE DFP2INT is the pipelined floating point to integer converter. The input and output numbers format is according to IEEE-754 standard. DFP2INT supports single precision real numbers and double word integers (4 Bytes). Convert operation is pipelined to 2 levels. Input data are fed every clock cycle. The first result appears after latency equal to 2 clock periods and next results are available each clock cycle. Full precision and accu-racy are accomplished.

Device Family Support

Virtex-4 FX

Virtex-4 LX

Virtex-4 SX

Virtex-II Pro

Spartan-3L

Spartan-3E

Spartan-3

Key Features

Full IEEE-754 compliance.

Single precision real input numbers.

Double word output numbers (4 Bytes).

Results available at every clock.

Overflow, underflow and invalid operation flags.

Fully configurable.

Fully synthesizable, static synchronous design with no internal tri-states."

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