Poll

What is your preferred platform for FPGA Design Flow ?:

Floating Point Divider

IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
Math
IP Supported FPGA Device: 
Spartan-3A
Spartan-3E
Spartan-IIE
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-II Pro
IP Description: 

"The AllianceCORE DFPDIV uses the pipelined mathematics algorithm to divide two arguments. The input numbers format is according to IEEE-754 standard. DFPDIV supports single precision real number. Divide operation was pipelined up to 21 levels. Input data are fed every clock cycle. The first result appears after 21 clock periods latency and next results are available each clock cycle. Full IEEE-754 precision and accuracy are included.

Device Family Support

Virtex-4 FX

Virtex-4 LX

Virtex-4 SX

Virtex-II Pro

Spartan-3L

Spartan-3E

Spartan-3

Spartan-IIE

Key Features

Full IEEE-754 compliance

Single precision real format numbers

Simple interface

Results available at every clock

Overflow, underflow and invalid operation flags

Fully configurable

Fully synthesizable, static synchronous design with no internal tri-states"

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