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Floating Point Arithmetic Unit

IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Math
IP Supported FPGA Device: 
Stratix
Stratix II
Stratix II GX
Stratix III
IP Description: 

"Features
Direct replacement for C float software functions such as: +, -, *, /,==, !=,<=, <=, <,>
C interface supplied for Altera® Nios® embedded processors, 8051 compilers
No programming required
Single precision real format support-float type
Flexible arguments and result registers location
Performs the following functions:
FADD, FSUB—addition, subtraction
FMUL, FDIV—multiplication, division
FSQRT—square root
FCHS, FABS—change of sing, absolute value
FXAM—examine input data
FUCOM—comparison
Exceptions built-in routines
Masks each exception indicator
Precision lack PE
Underflow result UE
Overflow result OE
Invalid operand IE
Division by zero ZE
Denormal operand DE
Fully synthesizable, static synchronous design with no internal tri-states
Optimized for use with the Nios embedded processors

Description
DFPAU uses the specialized algorithms to compute arithmetic functions. It supports addition, subtraction, multiplication, division, square root, comparison, absolute value, and change sign of a number. DFPAU supports single precision real numbers of IEEE-754 standard. DFPAU is well-suited for use with the 32-bit Nios processor."

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