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FIR Filter using DPRAM

IP Vendor: 
eInfochips Ltd.
IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
DSP - Digital Signal Processing
IP Supported FPGA Device: 
Spartan-IIE
Virtex
Virtex-E
Virtex-II
IP Description: 

"The eInfochips generic FIR filter core provides optimal results for a higher number of taps. It has 80 I/O pins and the user can change the coefficients at run time. Only a single Signed Multiplier unit is used. It accepts 16-bit signed sampled inputs and 16-bit signed coefficients. 32-bit signed outputs of the multiplier is supplied to an adder which is working on pipeline concept. The final output of an adder can achieve up to 32-bit precision.

Device Family Support

Virtex-II

Virtex-E

Virtex

Spartan-IIE

Spartan

Key Features

Up to 1024 taps

16-bit input and coefficient data precision

32-bit output data

Uses dual-port RAM for sample and coefficient data storage"

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