Poll
What is your preferred platform for FPGA Design Flow ?
Windows
54%
Linux
37%
Solaris
1%
Mixed
3%
Other
1%
No preference
4%
Total votes: 3278
FIR Filter, Parallel Distributed Arithmetic
IP Vendor:
eInfochips Ltd.
IP Target Vendor:
Xilinx
IP Type:
Design
IP Category:
DSP - Digital Signal Processing IP Supported FPGA Device:
Spartan-IIE
Virtex
Virtex-E
Virtex-II
IP Description:
"The eInfochips FIR filters are one of the most basic building blocks used in digital signal processing, taxing the performance that DSP hardware can deliver.
Device Family Support
Virtex-II
Virtex-E
Virtex
Spartan-IIE
Spartan
Key Features
Up to 1024 taps
24-bit output and coefficient data precision
16-bit input data
Parallel Distributed Arithmetic (PDA) architecture
Signed arithmetic"








