What is your preferred platform for FPGA Design Flow ?:

FIR Filter Generator

IP Vendor: 
IP Target Vendor: 
IP Type: 
IP Category: 
DSP - Digital Signal Processing
IP Description: 


Variable Number of Taps, up to 2048
Input and Coefficients Widths of 2 to 36 Bits
Selectable Rounding: Truncation, Round to Nearest, Convergent Rounding
Optional Saturation Logic for Overflow Handling
Full Precision Arithmetic
Signed or Unsigned Data and Coefficients
Configurable Parallelism from Full to Single Multiplier
Multi-channel Support (up to 256 Channels)
Decimation and Interpolation Ratios from 2 to 256
Configurable Pipelining to Increase Performance
Specification of Fractional Inputs and Outputs
Optional External Memory Interface for Data and Coefficients
Multi-channel Operation with Per-channel Coefficients and Parameters
Channel_in/channel_out Ports to Facilitate System Timing

Facebook  Twitter  Linkedin  YouTube      RSS


Check out FPGA related videos

Find Us On Facebook