Poll

What is your preferred platform for FPGA Design Flow ?:

Fast Color JPEG Decoder

IP Vendor: 
Barco-Silex
IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Audio, Video and Image Processing
IP Supported FPGA Device: 
Cyclone II
Stratix
Stratix II
IP Description: 

"Features
High-speed sustained single clock cycle per pixel component decoding
Single clock cycle Huffman decoding
APEXâ„¢ 20KC and APEX II optimized support
100% baseline ISO/IEC 10918-1 JPEG compliance for gray-scale images (single- and multi-scan formats) extending to effective 256-scan support
Full header parsing capability and automatic on-the-fly Huffman and quantization tables reprogramming from header data
Header error catching features
Full JPEG format and abbreviated format support, including restart markers
Simple first-in, first-out (FIFO) interfaces for compressed data (32 bits) and pixel interfaces (8 bits)
Simple CPU interface for decoder programming
Easy-to-use status and control interface through six internal registers
Programmable external interrupt for event follow-up
Four entropy tables (two DC, two AC) and four quantization tables
Burst image-sequence decoding support for images with identical tables
8 bits/pixel
8 x 8 block-format pixel output with classical scan order (row by row from left to right)
Fully synchronous hardware design
Fully stallable compressed-data interface; stallable pixel interface on a block-by-block basis
IEEE 1180-1990 compatible IDCT for number precision requirements

Description
The JPEG IP core is intended for high-speed decoding of gray-scale, color, or multi-scan images coded with ISO/IEC 10918-1 baseline coding standard. The decoder supports all features of the baseline standard, including restart markers and full header parsing. It is able to decode abbreviated-format or full-format images, automatically extracting the quantization and entropy tables.

With its autonomous behavior, simple FIFO-like interfaces, and 100% synchronous structure, you can integrate this IP core in a complex system with little effort. This is reinforced by the stand-alone ability of the decoder that allows to instantiate it in systems without CPU intervention."

Facebook  Twitter  Linkedin  Orkut  YouTube      RSS

 

Check out FPGA related videos

Find Us On Facebook