Home
World's Largest FPGA/CPLD Portal


Poll

What is your preferred platform for FPGA Design Flow ?
Windows
54%
Linux
37%
Solaris
1%
Mixed
3%
Other
1%
No preference
4%
Total votes: 3278

Ethernet MAC, 10/100 (MAC)

IP Vendor: 
CAST, Inc.
IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
Communication and Networking
IP Supported FPGA Device: 
Spartan-3
Spartan-IIE
Virtex-II
Virtex-II Pro
IP Description: 

"The AllianceCORE MAC from CAST is a high-speed LAN controller that implements Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms defined by the IEEE 802.3 standard for media access control over Ethernet. Communication with an external host is implemented via a set of Control and Status Registers and the DMA controller for external shared RAM memory. For data transfers the MAC operates as a DMA master. It automatically fetches from transmit data buffers and stores receive data buffers into external RAM with minimum CPU intervention. The linked list management enables the use of various memory allocation schemes. There is an interface for external dual port RAMs serving as configurable FIFO memories and there are separate memories for transmit and receive processes. Using the FIFOs additionally isolates the MAC from an external host and provides resolution in case of latency of an external bus.

Device Family Support

Virtex-II Pro

Virtex-II

Spartan-3

Spartan-IIE

Key Features

Network interface features; supports 10/100Mb/s data transfer rates, media Independent Interface (MII)

Data link layer functionality; meets the IEEE 802.3 CSMA/CD standard, full or half duplex operation, flexible address filtering, external RAM for storing MAC addresses, up to 16 physical addresses, 512 bit hash table for multicast addresses

Control and status registers; configurable 8/16/32 bit slave interface, single interrupt line, interrupt mitigation control mechanism

DMA controller; configurable 8/16/32 bit data bus length, configurable address bus length, big or little endian data byte ordering, scatter/gather capabilities, programmable burst length, intelligent arbitration between transmit and receive processes

Descriptor/buffer architecture for data storage; descriptor ""ring"" or ""chain"" structures, automatic descriptor list pooling

Transmit/Receive dual port RAM interfaces; operate as internal configurable FIFOs, programmable threshold levels, ""store and forward"" functionality"

Facebook  Twitter  Linkedin  Orkut  YouTube      RSS

Check out FPGA related videos

Find Us On Facebook