Poll

What is your preferred platform for FPGA Design Flow ?
Windows
55%
Linux
36%
Solaris
1%
Mixed
2%
Other
1%
No preference
4%
Total votes: 4721

EP510: CompactFlash/PCMCIA Host Adapter

IP Vendor: 
Eureka Technology
IP Target Vendor: 
Lattice
IP Type: 
Design
IP Category: 
Memory Interface and Storage Element
IP Description: 

"The host adapter supports all four access types as defined in the PC Card/PCM-CIA/ CompactFlash standards, including memory and IO access for ISA bus, common memory, attribute memory and IO access for PC Card/PCMCIA/The host adapter allows host CPU to access the PC Card/PCMCIA and CompactFlash cards. Different options of user interfaces are available. In the most basic form, the core contains a simple user interface which is optimized for on-chip connections. The user interface is modeled after generic microprocessor interface.

The core can also be integrated with other CPU bus slaves to interface directly with other embedded CPUs. The CPU supported are ARM (with AMBA AHB bus), PowerPC (with 60X bus or MPC860 bus), MIPS (with SysAD bus or EC interface), ARC and Hitachi SH2, SH3 and SH4 embedded processors.

The host adapter supports different types common memory access, attribute memory access and IO access for PC Card/PCMCIA/CompactFlash. It also supports True IDE mode in CompactFlash. Different chip select signal is provided for the CPU or user logic to select the address space being accessed.

The basic CPU interface can be 32 or 64-bit while the card interface can be either 8-bit or 16-bit. It supports burst and single data access by the CPU. When the CPU request reading of 32-bit of data from the card, the host adapter performs multiple 8-bit or 16-bit read operation to collect 32-bit data for the CPU. When the CPU writes 32-bit data to the card, the host adapter performs multiple 8-bit or 16-bit write to the card to write all the data. Burst access is not supported by the host adapter.

Direct address mapping is provided by the host adapter with address space selected by chip select input signals. Customized address translation scheme can be provided upon customer request.

The host adapter operates on two clock domains, the user interface clock domain and the card interface clock domain. All I/O signals on the user interface are timed by the rising edge of the user interface clock. All I/O signals on the card interface are timed by the rising edge of the card interface clock. Request/Acknowledge and double synchronization are used when transfer data between the clock domains. This design approach allows the user interface to run at the higher CPU bus clock frequency while the card interface runs at a lower clock frequency."

Facebook  Twitter  Linkedin  YouTube      RSS

 

Check out FPGA related videos

Find Us On Facebook