Poll

What is your preferred platform for FPGA Design Flow ?:

EP300: PowerPC Bus Arbiter

IP Vendor: 
Eureka Technology
IP Target Vendor: 
Lattice
IP Type: 
Design
IP Category: 
Bus Interface and IO
IP Description: 

"Features
Fully supports PowerPCTM 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260.
Supports up to eight PowerPC bus masters with unlimited slave device support.
Supports two outstanding bus accesses.
Supports address only transfer and address bus retry.
Independent address bus and data bus tenure with separate bus grant and data bus grant.
Option for fixed priority assignment or rotating priority scheme.
Designed for ASIC or programmable logic device implementations in various system environments.
Fully static design with edge triggered flip-flops.
Optimized for ispXPGA product family."

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