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EP201: PowerPC Bus Master

IP Vendor: 
Eureka Technology
IP Target Vendor: 
Lattice
IP Type: 
Design
IP Category: 
Bus Interface and IO
IP Description: 

"The PowerPC bus master is a bus interface unit designed for the PowerPC host bus. It allows the user to initiate data transfer directly on the PowerPC CPU bus through a very simple user interface.

The PowerPC bus master arbitrates for the PowerPC address bus before starting any transfers. It handles separate address and data bus tenure so that data bus is arbitrated independently from the address bus. The bus master handles address retry by the CPU or other sources on the CPU bus. Upon address retry, it automat-ically re-starts the data transfer unless an error has occurred.

Single beat, burst data and extended MPC8260 data transfer are supported. Differ-ent data size and transfer types are allowed and can be specified through an inter-nal back-end bus. There are two user interface ports provided by the bus master. It allows two different devices to access the PowerPC bus through a single bus mas-ter. The bus master contains arbitration logic to arbitrate between the two request ports."

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