Poll

What is your preferred platform for FPGA Design Flow ?
Windows
55%
Linux
36%
Solaris
1%
Mixed
2%
Other
1%
No preference
4%
Total votes: 4742

DSPI Serial Peripheral Interface Master/Slave

IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Bus Interface and IO
IP Supported FPGA Device: 
Apex 20KC
Apex 20KE
Apex II
Excalibur
Flex 10KE
Stratix
IP Description: 

"Features
Serial peripheral interface (SPI) Master
Master and multi-Master operation
System error detection
Mode fault error
Write collision error
Interrupt generation
Supports speeds up to 1/4 of system clock
8 Slave select lines
Bit rates generated 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, and 1/512 of system clock
Four transfer formats supported
Simple interface allows easy connection to microcontrollers
SPI Slave
Slave operation
System error detection
Interrupt generation
Supports speeds up 1/4 of system clock
Simple interface allows easy connection to microcontrollers
Four transfer formats supported
Fully synthesizable, static synchronous design with no internal tri-states
Technology independent hardware description language (HDL) source code

Description
The DSPI core is a fully configurable SPI Master/Slave devicethat allows user to configure polarity and phase of serial clock signal SCK.

The DSPI allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. DSPI data is simultaneously transmitted and received.

The DSPI core is a technology-independent design that can be implemented in a variety of process technologies.

The DSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a Master or a Slave device. Data rates are as high as 1/4 of the clock rate. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a Master, software selects one of four different bit rates for the serial clock.

The DSPI core automatically drives-controlled by the slave select control register (SSCR)-slave select outputs (SS7O-SS0O) and addresses the SPI slave device to exchange serially shifted data. Error-detection logic is included to support interprocessor communications. A write-collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master modefault detector automatically disables DSPI output drivers if more than one SPI device simultaneously attempts to become bus master."

Facebook  Twitter  Linkedin  YouTube      RSS

 

Check out FPGA related videos

Find Us On Facebook