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What is your preferred platform for FPGA Design Flow ?:

DP8051: Pipelined High Performance 8-bit MCU

IP Vendor: 
Digital Core Design
IP Target Vendor: 
Lattice
IP Type: 
Design
IP Category: 
Embedded Processing
IP Description: 

Features

100% software compatible with industry standard 8051
Pipelined RISC architecture enables to execute instructions 10 times faster compared to standard 8051
24 times faster multiplication
12 times faster addition
Up to 256 bytes of internal (on-chip) Data Memory
Up to 64K bytes of internal (on-chip) or external (off-chip) Program Memory
Up to 16M bytes of external (off-chip) Data Memory
User programmable Program Memory Wait States solution for wide range of memories speed
User programmable External Data Memory Wait States solution for wide range of memories speed
De-multiplexed Address/Data bus to allow easy connection to memory
Dedicated signal for Program Memory writes.
Interface for additional Special Function Registers
Fully synthesizable, static synchronous design with positive edge clocking and no internal tri-states
Scan test ready
2.0 GHz virtual clock frequency in a 0.35µ technological process"

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