DO-254 IP : PCI Express Endpoint
PCI Express® Endpoint Gen 1 at 2.5 Gbps.
One Lane (x1).
PIPE: 16 bits interface (Optional 8 bits). PIPE Clock frequency is 250MHz in 8 bits or 125MHz in 16 bits.
AMBA AXI4: 32 bits data/address Slave and Master Interfaces (Optional APB interface for Configuration Registers).
Supports 6 BAR (Base Address Registers).
Supports PCIe Power Management capability: ASPM L0s and L1.
Optional MSI capabilities.
Full AER capability implemented.
Full report done to Root Complex and to user application. (ECC on data buffers, FSM monitoring)
Implements Advanced Reliability features for critical applications.
Optional CDC between PCIe’s clock domain and AXI’s clock domain.
Optimized for low gate count (4-5k LE on FPGA) and low core latency.
Configurable buffer size from 512B to 2kB depending on performance requirement.
The PCI Express protocol has become increasingly popular as the PCI bus successor for IO device attachment. While PCI Express utilizes advanced fast serial interconnect technologies for improved performance, it retains the successful configuration and programming model of the existing PCI protocol, allowing integration of PCIe devices without requiring specific software support.
While retaining full backward compatibility with current software, PCI Express introduces many new features, allowing advanced system diagnostics and error recovery, power management, and traffic differentiation.