DO-254 IP : PCI Express Endpoint

PCI Express® Endpoint Gen 1 at 2.5 Gbps.
One Lane (x1).
PIPE: 16 bits interface (Optional 8 bits). PIPE Clock frequency is 250MHz in 8 bits or 125MHz in 16 bits.
AMBA AXI4: 32 bits data/address Slave and Master Interfaces (Optional APB interface for Configuration Registers).
Supports 6 BAR (Base Address Registers).
Supports PCIe Power Management capability: ASPM L0s and L1.
Optional MSI capabilities.
Full AER capability implemented.
Full report done to Root Complex and to user application. (ECC on data buffers, FSM monitoring)
Implements Advanced Reliability features for critical applications.
Optional CDC between PCIe’s clock domain and AXI’s clock domain.
Optimized for low gate count (4-5k LE on FPGA) and low core latency.
Configurable buffer size from 512B to 2kB depending on performance requirement.