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DO-254 IP : Ethernet Endpoint

IP Vendor: 
DMAP S.A.R.I.
IP Target Vendor: 
Other
IP Code Language: 
Verilog
IP Type: 
Design
IP Category: 
Communication and Networking
IP Description: 

Tri-Mode 10/100/1000 Fully integrated Ethernet MAC in Full-duplex.
Supports Preamble, SFD and frame padding generation, CRC on both Rx and Tx path.
Support for VLAN tagged frames according to IEEE 802.1Q and 9kB jumbo frame.
Configurable to support 10Mbps, 100Mbps or 1Gbps operation.
32 bits simple FIFO interface to user application compatible with simple FIFO interface.
User interface for Configuration Registers and status information (VLAN tag, frame type and errors).
GMII (125MHz) or MII (25MHz) interface to Ethernet PHY device.
Full report done to remote peer and to SoC. (Parity on data buffers, FSM monitoring).
CRC-32 with optional forwarding of the FCS field.
Autonomous and dynamically configurable XON/XOFF Pause Frame (802.3 Annex 31A) support.
Optimized for low gate count (20k-40k gates) and low core latency. Technology independent (Altera/Xilinx/Actel/ASIC).
Configurable buffer size from 64B to 16kB depending on performance requirement.
Optional support of AMD Magic Packet detection for node remote power management.
Support multiple MAC address filtering and multicast address filtering on Rx path with hash table.

Ethernet is standardized as IEEE 802.3. The combination of the twisted pair versions of Ethernet for connecting end systems to the network, along with the fiber optic versions for site backbones, is the most widespread wired LAN technology. It has been used from around 1980[1] to the present.
The programmable 10/100/100 Ethernet MAC from MorethanIP provides, with a single IP Core, a solution for Ethernet applications (Line Card, NIC card or switching) operating at 10/100 or 1000Mbps (Gigabit Ethernet). The 10/100/1000 MAC Core operates Full Duplex mode, supports transparent (For switching applications) and full Ethernet frame termination / generation (For NIC or line cards applications). For efficient power management, the Core also implements Magic Packets detection. The core can seamlessly connect to any industry standard Gigabit Ethernet PHY device via a Gigabit Medium Independent Interface (GMII for 1000Mbps application) or Medium Independent Interface (MII for 10/100Mbps applications) and to a user application via a SOC (System on a Chip) interface which provides seamless connectivity to any MorethanIP.

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