What is your preferred platform for FPGA Design Flow ?:

DO-254 IP : ARINC429

IP Vendor: 
IP Target Vendor: 
IP Code Language: 
IP Type: 
IP Category: 
Bus Interface and IO
IP Description: 

Clock frequency configurable in 1 MHz, 10 MHz, 16 MHz or 20 MHz
512 bytes of APB address space
Rx and Tx ARINC429 Channels number independently configurable from 1 to 16
ARINC429 input and output configurable in Low (12.5 kHz or 50 kHz) or High (100 kHz) speed mode
One FIFO for each ARINC429 channel
ARINC429 channel FIFO depth configurable in 32, 64, 128, 256 or 512 bits
APB_ARINC429 IP supports up to 256 unique labels per Receive channel
AMBA APB Read data bus width and Write data bus width configurable in 8, 16 or 32 bits
A support Source/Direction Identifiers mechanism per Receive channel
A loopback mode for safety and testing purpose
Supporting the main Actel® device families (proASIC+, etc…)

ARINC 429 is the technical standard for the avionics data bus used on most higher-end commercial and transport aircraft. It defines the physical and electrical interfaces of a two-wire data bus and a data protocol to support an aircraft's avionics local area network. The support of a Label mechanism is provided as part of the ARINC 429 specification, for various equipment types. Each aircraft will contain a number of different systems, such as flight management computers, inertial reference systems, air data computers, radar altimeters, radios, and GPS sensors. For each type of equipment, a set of standard parameters is defined, which is common across all manufacturers and models.
ARINC 429 is a two-wire, point-to-point data bus that is application-specific for commercial and transport aircraft. The connection wires are twisted pairs. Words are 32 bits in length and most messages consist of a single data word. The specification defines the electrical standard and data characteristics and protocols. ARINC 429 uses a unidirectional data bus standard (Tx and Rx are on separate ports) known as the Mark 33 Digital Information Transfer System (DITS). Messages are transmitted at 12.5, 50 (optional), or 100 kbps to other system elements that are monitoring the bus messages. The transmitter is always transmitting either 32-bit data words or the Null state.

Facebook  Twitter  Linkedin  YouTube      RSS


Check out FPGA related videos

Find Us On Facebook