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DI2CM I2C Bus Interface-Master

IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Bus Interface and IO
IP Supported FPGA Device: 
Apex 20KC
Apex 20KE
Apex II
Excalibur
Flex 10KE
Stratix II
IP Description: 

"Features
Master operation
Multi-master systems supported
Performs arbitration and clock synchronization
Interrupt generation
Supports speeds up to 3.4 Mbits per second (standard, fast, and high-speed mode)
Allows operation from a wide range of input clock frequencies (built-in 8-bit timer)
User-defined timing
Fully synthesizable, static synchronous design with no internal tri-states

Description
The DI2CM function provides an interface between a microprocessor and an I2C bus. The function can be programmed to operate with arbitration and clock synchronization in multi-master systems. The DI2CM function can be used in automotive audio-video systems and embedded microprocessor systems."

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