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Poll
DFPSQRT: Floating Point Pipelined Square Root Unit
IP Vendor:
Digital Core Design
IP Target Vendor:
Lattice
IP Type:
Design
IP Category:
DSP - Digital Signal Processing IP Description:
Full IEEE-754 compliance
Single precision real format support
Simple interface
No programming required
9 levels pipeline
24-bit accuracy, 6 fractional decimal digits
Results available at every clock
Fully configurable
Fully synthesizable, static synchronous design with no internal tri-states
Applications
Math coprocessors
DSP algorithms
Embedded arithmetic coprocessor
Data processing & control
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