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DFPMU Floating-Point Mathematics Unit

IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Math
IP Supported FPGA Device: 
Acex 1K
Apex 20KC
Apex 20KE
Apex II
Excalibur
Stratix
Stratix II
IP Description: 

"Features
Direct replacement for C float software functions that include: +, -, *, /,==, !=,>,=, <=, <, >
C interface supplied for Nios® embedded processors and 8051 compilers
No programming required
Single precision real format support - float type
16-bit word and 32-bit short integer format supported - integer types
Flexible arguments and result registers
Performs the following functions:
Addition, subtraction
Multiplication, division
Square root
Change of sine, absolute value
Examine input data, comparison
Sine, cosine, tangent, and arctangent
16-bit, 32-bit integer to float
Exceptions built-in routines
Masks each exception indicator:
Precision lack (PE)
Underflow result (UE)
Overflow result (OE)
Invalid operand (IE)
Division by zero (ZE)
Denormal operand (DE)
Fully synthesizable, static synchronous design with no internal tri-states
Optimized for use with Altera® Nios embedded processor

Description
DFPMU uses the specialized CORDIC and standard algorithms to compute math functions. It has built-in conversion instructions that will convert integer types to floating point types and vice versa. DFPMU supports single precision real numbers, and 16- and 32-bit integers. The input numbers format is in accordance with the IEEE-754 standard and can be used with the 32-bit Nios embedded processor."

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