Poll
What is your preferred platform for FPGA Design Flow ?
Windows
55%
Linux
36%
Solaris
1%
Mixed
2%
Other
1%
No preference
4%
Total votes: 4840
DFPADD: Floating Point Pipelined Adder Unit
IP Vendor:
Digital Core Design
IP Target Vendor:
Lattice
IP Type:
Design
IP Category:
DSP - Digital Signal Processing IP Description:
Features
Full IEEE-754 compliance
Single precision real format support
Simple interface
No programming required
5 levels pipeline
Full accuracy and precision
Results available at every clock
Overflow, underflow and invalid operation flags
Fully configurable
Fully synthesizable, static synchronous design with no internal tri-states
Applications
Math coprocessors
DSP algorithms
Embedded arithmetic coprocessor
Data processing & control
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