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DF6811CPU 8 Bit Microcontroller CPU

IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Embedded Processing
IP Supported FPGA Device: 
Acex 1K
Apex 20KC
Apex 20KE
Apex II
Excalibur
Flex 10KE
Stratix
Stratix II
IP Description: 

"Features
Software compatible with industry-standard 68HC11
FAST architecture, 3.8 times faster than the original implementation
10 times faster multiplication
16 times faster division
64 bytes of remapped system function registers space (SFRs)
Up to 16 Mbytes of data memory
De-multiplexed address/data bus to allow easy connection to memory
Interrupt Controller
Non-maskable XIRQ pin interrupt
Maskable IRQ pin interrupt
Illegal opcode interrupt
Two power-saving modes: STOP, WAI
User-programmable external data memory write and read pulses between 1 to 8 clock periods
Fully synthesizable, static synchronous design with no internal tri-states
No internal reset generator or gated clock
Scan-test ready
Technology-independent hardware description language (HDL) source code

Description
The DF6811CPU is an advanced 8-bit MCU IP with highly sophisticated, on-chip peripheral capabilities. DF6811CPU soft core is binary-compatible with the industry-standard 68HC11 8-bit microcontroller and can achieve a performance of up to 25 million instructions per second in today's integrated circuit technologies. DF6811CPU has FAST architecture that is 3.8 times faster compared to original implementation.

Self-monitoring circuitry is included on-chip to protect against system errors. An illegal op-code detection circuit provides a non-maskable interrupt if illegal opcode is detected.

Two software-controlled power-saving modes, WAIT and STOP, are available to con-serve additional power. These modes make the DF6811CPU IP Core especially attractive for automotive and battery-driven applications.

The DF6811CPU has built-in development features. The LIR signal is intended as a debugging aid. This signal is driven to active low for the first bus cycle of each new instruction, making it easy to reverse assemble (dis-assemble) instructions from the display of a logic analyzer."

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