Poll

What is your preferred platform for FPGA Design Flow ?:

UART

IP Vendor: 
Develeast
IP Code Language: 
VHDL
IP Type: 
Design
IP Category: 
Bus Interface and IO
IP Description: 

KEY FEATURES:
- Compliant to the TIA-232-F
- Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
- Configurable baud rate, number of data bits, parity and stop bits
- Error detection (parity and form)
- Simple interface to user's logic
- TMR coded for SEU immunity (optional)
- Technology independent (can be synthesized to any FPGA/CPLD vendor)

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