Poll

What is your preferred platform for FPGA Design Flow ?:

SPI Master BFM

IP Vendor: 
Develeast
IP Code Language: 
VHDL
IP Type: 
Verification
IP Category: 
Bus Interface and IO
IP Description: 

KEY FEATURES:
- Compliant to SPI Standard (Motorola's M68HC11 Reference Manual)
- Configurable data rate
- Configurable phase, polarity and word size
- Configurable number of slaves (Slave Select)
- Simple interface to user's logic
- Technology independent (can be used with any simulation tool)

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