Poll

What is your preferred platform for FPGA Design Flow ?:

CAN Core

IP Vendor: 
Develeast
IP Code Language: 
VHDL
IP Type: 
Design
IP Category: 
Bus Interface and IO
IP Description: 

KEY FEATURES:
- Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
- Compliant to CAN Specification Version 2.0B (Sep 1999)
- Time Triggered Communication (TTC) support according to ISO 11898-1 (2003-12-01)
- Tested as specified in the ISO 16845 (2004-03-15)
- Configurable data rate
- Interfaces to standard transceivers
- Simple interface to user's logic
- TMR coded for SEU immunity (optional)
- Technology independent (can be synthesized to any FPGA/CPLD vendor)

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