Poll

What is your preferred platform for FPGA Design Flow ?:

ARINC 429 Receiver

IP Vendor: 
Develeast
IP Code Language: 
VHDL
IP Type: 
Design
IP Category: 
Bus Interface and IO
IP Description: 

KEY FEATURES:
- Compliant to ARINC Specification 429-17 (May 17, 2004)
- Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
- Configurable data rate and tolerance
- Multiple error checking (frequency, gap, parity and form)
- Interfaces to standard line receivers
- Simple interface to user's logic
- TMR coded for SEU immunity (optional)
- Technology independent (can be synthesized to any FPGA/CPLD vendor)

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