Poll
DES Encryption
"The DES core is a fully compliant implementation of the DES encryption algorithm, suitable for a variety of applications. Both encryption and decryption are supported. CBC, CFB, OFB and Triple DES versions are also available. Developed for easy reuse in ASIC and FPGA applications, DES is available optimized for several technologies with competitive utilization and performance characteristics.
Device Family Support
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-II Pro
Spartan-3E
Spartan-3
Spartan-IIE
Key Features
NIST certified 56-bit DES implementation.
Encryption and decryption performed in 16 clock cycles.
No dead cycles for key loading or mode switching.
Suitable for Electronic Codebook (ECB), Cipher Block Chaining (CBC), Cypher Feed Back (CFB) and Output Feed Back (OFB) implementations.
Triple DES implementations available.
Sustained bit rate is 4 x clock speed.
High clock speed and low gate count achieved."
Check out FPGA related videos
Find Us On Facebook
FPGA Central is a website bringing the FPGA (Field Programable Gate Array), CPLD , PLD, VLSI community together at one central location. Some Keywords: FGPA, FPGA, EDA Tools, FPGA Design, Central, Programmable logic, LUT, VLSI, SoC, Journal
Privacy Policy || Terms of Use
 |
 |