Poll

What is your preferred platform for FPGA Design Flow ?:

DES and DES3 Encryption Engine

IP Vendor: 
Avnet
IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
Communication and Networking
IP Supported FPGA Device: 
Spartan-IIE
Virtex
Virtex-E
Virtex-II
IP Description: 

"The Memec Design MC-XIL-DES Data Encryption Standard engine core provides a scalable hardware implementation of the data encryption standard (DES). Its ease of use and high performance makes it a cost competitive solution to dedicated hardware or software alternatives. DES is a block-oriented encryption algorithm. Plain-text data is loaded 64 bits at a time, along with the encryption key. Encrypted ciphertext is available 16 clocks cycles later for single-DES operation. The same solution can be used for both single and triple DES operation.

Device Family Support

Virtex-II

Virtex-E

Virtex

Spartan-IIE

Spartan

Key Features

NIST certified

Supports EBC, CBC, CFB, and OFB"

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