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DDR2 SDRAM High Performance Controller

IP Vendor: 
Altera
IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Memory Interface and Storage Element
IP Supported FPGA Device: 
Cyclone III
Stratix II
Stratix II GX
Stratix III
IP Description: 

"Features
Supports:
Industry-standard DDR/DDR2 SDRAM devices and modules
Complete DDR/DDR2 solution available by bolting onto ALTMEMPHY physical interface megafunction
Optional user-controller refresh
Usage:
Optional Avalon® Memory-Mapped local interface
Support for OpenCore Plus evaluation
Easy-to-use MegaWizard® interface
IP functional simulation modules for use in Altera-supported VHDL and Verilog HDL simulators
General Description
The Altera DDR and DDR2 SDRAM High-Performance Controller MegaCore® functions provide simplified interfaces to industry-standard DDR SDRAM and DDR2 SDRAM. The MegaCore functions work in conjunction with the Altera ALTMEMPHY physical interface megafunction. This DDR and DDR2 SDRAM MegaCore functions support Stratix® II, Stratix II GX, Stratix III and Cyclone III devices. The controllers offer a half rate interface to the customer application logic. As an example, for Stratix III devices, the DDR2 SDRAM High-Performance Controller MegaCore® function enables an interface up to 800 Mbps/400 MHz to the external memory while presenting a 200-MHz interface to the customer application logic. Similarly for Cyclone III devices, the DDR2 SDRAM High-Performance Controller MegaCore® function enables an interface up to 400 Mbps/200 MHz to the external memory while presenting a 100-MHz interface to the customer application logic

The MegaWizard Plug-In Manager generates an example design, instantiates a phase-locked loop (PLL), an example driver, your DDR or DDR2 SDRAM controller custom variation, and an optional DLL (for Stratix series only). The example design is a fully-functional design that can be simulated, synthesized, and used in hardware. The example driver is a self-test module that issues read and write commands to the controller and checks the read data to produce the pass/fail and test complete signals. Figure 1 shows a system-level diagram including the example design that the DDR or DDR2 SDRAM Controller MegaCore functions create for you."

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