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What is your preferred platform for FPGA Design Flow ?:

DDR2 SDRAM Controller - Pipelined

IP Vendor: 
Lattice
IP Target Vendor: 
Lattice
IP Type: 
Design
IP Category: 
Memory Interface and Storage Element
IP Description: 

Interfaces to Industry Standard DDR2 SDRAM
High-Performance DDR2 533/400/333/266/200/133 operation
Programmable Burst Lengths of 4 or 8
Programmable CAS Latency of 3, 4, 5 or 6 Cycles
Intelligent Bank Management to Minimize ACTIVE Commands
Supports All Standard DDR Commands
Synchronous Implementation for Reliable Operation
Command Pipeline to Maximize Throughput
Up to 4 chip selects for multiple DIMM support
Supports all Common Memory Configurations
SDRAM data path widths of 8, 16, 32, 64 and 72 bits
Variable address widths for different memory devices
Programmable timing parameters
Byte level writing through Data Mask signals
Burst termination"

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