DDR2 SDRAM Controller

"Features
Support for industry-standard DDR/DDR2 SDRAM devices and modules
Including support for registered DIMMs
Flexible, robust design
1, 2, 4, or 8 chip-select signals
Configurable data width with data strobe (DQS) read postamble control logic and optional non-DQS read mode for side banks for Stratix® series devices.
Automatic or user-controlled refresh
Data mask signals for partial write operations
Bank management architecture, which minimizes latency
Quick and easy implementation
IP Toolbench-generated constraint script
Top-level example design shipped as a deliverable with the IP MegaCore® function
IP functional simulation models used in Altera-supported VHDL and Verilog HDL simulators
Free clear-text data path for use with custom controller
SOPC Builder ready to enable system-level design
General Description
The DDR and DDR2 SDRAM Controllers handle the complex aspects of using DDR/DDR2 SDRAM—initializing the memory devices, managing SDRAM banks, and keeping the devices refreshed at appropriate intervals. The controllers translate read and write requests from the local interface into all the necessary SDRAM command signals.

The DDR2 SDRAM Controller is optimized for Altera® Stratix III, Stratix II, Stratix II GX, and Cyclone® II devices while the DDR SDRAM Controller is optimized for Stratix III, Stratix II, Stratix II GX, Stratix, Stratix GX, Cyclone II, and Cyclone devices. The advanced features available in these devices allow you to interface directly to DDR/DDR2 SDRAM devices and to use the DQS signal in the read and write direction.

Whether you use IP Toolbench in SOPC Builder or the Quartus® II software, it generates an example design, instantiates a phase-locked loop (PLL), an example driver, your DDR/DDR2 SDRAM controller custom variation, and an optional DLL (for Stratix II devices only). The example design is a fully-functional example design that can be simulated, synthesized, and used in hardware. The example driver is a self-test module that issues read and write commands to the controller and checks the read data to produce the pass/fail and test complete signals.

You can replace the DDR/DDR2 SDRAM controller encrypted control logic in the example instance with your own custom logic, which allows you to use the Altera clear-text data path with your own control logic."