DDR SDRAM Controller - Pipelined

Features

Interfaces to Industry Standard DDR SDRAM
High-Performance DDR 400/333/266/200/133 operation for LatticeECP/EC, LatticeSC, LatticeECP2, and LatticeECP2M devices and DDR 333/266/200/133 operation for LatticeXP devices
Programmable Burst Lengths of 2, 4 or 8
Programmable CAS Latency of 2 or 3 Cycles
Intelligent Bank Management to Minimize ACTIVE Commands
Supports All Standard DDR Commands
Synchronous Implementation for Reliable Operation
Command Pipeline to Maximize Throughput
Support for Two DIMM
Supports all Common Memory Configurations
SDRAM data path widths of 8, 16, 32, 64 and 72 bits
Variable address widths for different memory devices
Programmable timing parameters
Byte level writing through Data Mask signals
Chip selects of 1, 2, 4 or 8 bits
Burst termination"