Poll
DA-FIR Filter Generator
"Features
Variable Number of Taps, up to 1024
Input and Coefficients Widths of 2 to 32 Bits
Selectable Rounding: Truncation, Round to Nearest, Convergent Rounding
Optional Saturation Logic for Overflow Handling
Full Precision Arithmetic
Signed or Unsigned Data and Coefficients
Support for both Serial and Parallel Filters, with User-Specified Degree of Parallelism
Multi-channel Support (up to 8 Channels)
Decimation and Interpolation Ratios from 2 to 8
Polyphase Interpolating/Decimating Filters
Configurable Pipelining to Increase Performance
Specification of Fractional Inputs and Outputs
Channel_out Ports to facilitate System Timing
Optimizations based on Filter Characteristics (Symmetry and Polyphase Halfband)"
Check out FPGA related videos
Find Us On Facebook
FPGA Central is a website bringing the FPGA (Field Programable Gate Array), CPLD , PLD, VLSI community together at one central location. Some Keywords: FGPA, FPGA, EDA Tools, FPGA Design, Central, Programmable logic, LUT, VLSI, SoC, Journal
Privacy Policy || Terms of Use
 |
 |