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What is your preferred platform for FPGA Design Flow ?:

D8254: Programmable Interval Timer

IP Vendor: 
Digital Core Design
IP Target Vendor: 
Lattice
IP Type: 
Design
IP Category: 
Embedded Processing
IP Description: 

Features

Three independent 16-bit counters
Six programmable Counter modes:
Interrupt on terminal count
Hardware retriggerable One-Shot
Rate Generator
Square wave mode
Software triggered strobe
Hardware triggered strobe
Binary or BCD counting
Status Read Back Command
Simple interface allows easy connection to microcontrollers
Fully synthesizable, static design with no internal tri-states"

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