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CUSB USB Function Controller

IP Vendor: 
CAST, Inc.
IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Bus Interface and IO
IP Supported FPGA Device: 
Cyclone II
Stratix
Stratix II
Stratix III
IP Description: 

"Features
Serial interface engine
Supports full-speed devices
Extraction clock and data signals in internal digital phase-locked loop (DPLL)
Non-return-to-zero-inverted (NRZI) decoding/encoding
Bit stuffing/stripping
Cyclic redundancy code (CRC) checking/generation
Interface for an external transceiver
Up to 31 configurable endpoints
Control transfers by endpoint 0
Bulk, interrupt, and isochronous transfers
Double buffering for isochronous endpoints
Programmable double buffering for bulk and interrupt endpoints
Automatic data retry mechanism
Data toggle synchronization mechanism
Suspend and resume power management functions
Remote wake-up function
Endpoint buffers RAM interface
2 by 1024 bytes FIFO buffer size for isochronous endpoints
Up to 64 bytes buffer size for each bulk, interrupt, and control endpoints
Microcontroller interface
Asynchronous address and data bus interfaces, and read and write control signals (internally synchronized within the CUSB core)
Interrupt request signals for application microcontroller
Interrupt vector for autovector interrupts
Description
The CUSB core is a universal serial bus (USB) function controller that provides a USB full-speed function interface that meets the USB Specification, Revision 1.1. The CUSB logic handles byte transfers autonomously and connects the USB interface to a simple read/write parallel interface. The CUSB function can be customized and optimized for a specific application. It contains a set of special function registers that is similar to the Cypress EZ-USB FX chip.

The CUSB function is a microcode-free design developed for reuse in ASIC and programmable logic implementations. The design is strictly synchronous with positive-edge clocking, no internal tri-states, and a synchronous reset."

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