Home
World's Largest FPGA/CPLD Portal


Poll

What is your preferred platform for FPGA Design Flow ?
Windows
54%
Linux
37%
Solaris
1%
Mixed
3%
Other
1%
No preference
4%
Total votes: 3278

CRC Compiler

IP Vendor: 
Altera
IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Basic Logic
IP Supported FPGA Device: 
Cyclone
Cyclone II
Cyclone III
Hardcopy II
Hardcopy Stratix
Stratix GX
Stratix II
Stratix II GX
Stratix III
IP Description: 

"Features
Highly parameterized Cyclic Redundancy Check (CRC) generator and checker
CRC-32, CRC-16-ANSI, and CRC-16-CCITT generator polynomials
High-speed operation, over 250 MHz for many configurations
Configurable input datapath width from 1 bit to 256 bits (power-of-two)
Configurable CRC starting value
Avalon® Streaming (Avalon-ST) interface for message/codeword bits
Support for all possible end-of-packet byte residues
Verilog and VHDL demonstration testbenches
Easy-to-use MegaWizard® interface
IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
Support for OpenCore Plus evaluation
General Description
The CRC Compiler generates high-performance circuits to generate or check Cyclic Redundancy Check (CRC) checksums for packet-based communication. The CRC generator uses an Avalon-ST interface to receive data and emits generated checksums on a dedicated output. The CRC checker similarly uses an Avalon-ST interface to receive a packet with a CRC checksum and uses a dedicated output to indicate if the checksum in correct. The CRC generator and checker MegaCore functions do not store any data, checksums, or status."

Facebook  Twitter  Linkedin  Orkut  YouTube      RSS

Check out FPGA related videos

Find Us On Facebook