The CS1024-RSA's synthesizable Verilog RTL uses a 32-bit multiplier and data path, which is the standard configuration. The RTL can be configured to use a 16-bit, 32-bit or 64-bit multiplier and data path.
Assuming an operating frequency of 200 MHz, the measured performance of the core is:
- 13586 modular exponentiations per second with exponent: 2^16 + 1 (Fermat's prime)
- 354 modular exponentiations per second (512-bit exponent, 50% 1's density)
- 177 “full exponent” modular exponentiation operations per second.
NOTE: The 512-bit and 1024-bit exponents have a random bit assortment with a 50% 1's density, a 1024-bit base and a 1024-bit modulus.
The CS1024-RSA is now available for evaluation by qualified clients.