CPRI

"The Lattice Common Public Radio Interface (CPRI) IP core together with SERDES and Physical Coding Sublayer (PCS) functionality integrated in the LatticeSCâ„¢ and LatticeECP2Mâ„¢ FPGAs implements the physical layer of the CPRI specification and interleaves IQ data with synchronization, control and management information. It can be used to connect Radio Equipment Control (REC) and Radio Equipment (RE) modules.

Features
Supports the physical link layer of the OBSAI RP3 specification
Supports the physical link layer (Layer 1) of the CPRI specification
Supports the three standard bit rates of the CPRI specification

614.4 Mbps
1228.8 Mbps
2457.6 Mbps
Supports 8b/10b encoding/decoding performed in the PCS/SERDES
Supports code-violation dectection performed in the PCS/SERDES
Performs CPRI Hyperframe Framing

Performs interleaving of IQ data, sync, C&M data, and vendor specific information
Provides an 8-, 16-, or 32-bit parallel interface for IQ data
Performs subchannel mapping:

Supports a slow C&M channel based on a serial HDLC interface at standard bit rates (240 Kbps, 480 Kbps, 960 Kbps, and 1920 Kbps). The HDLC framer, if needed, must be provided as a separate IP core.
Supports a fast C&M channel based on a serial Ethernet interface (84.48 Mbps max.) to the user logic and accepts a user selected pointer to the CPRI subchannel where the Ethernet link starts. The Ethernet MAC function must be provided as a separate IP core.
Performs synchronization and timing as defined in section 4.2.8 of the CPRI Specification
Supports the L1 Inband Protocol
Provides a parallel interface for merging vendor specific data into the CPRI frame
Supports Delay Calibration as defined in section 4.2.9 of the CPRI Specification
Provides a start-up sequence state machine in hardware for both REC and RE nodes which performs:

Synchronization and Rate Negotiation
C&M Plane setup
Performs Link Maintenance as defined in section 4.2.10 of the CPRI Specification:

LOS detection
LOF detection
RAI indication
Optional top-level template that implements user registers for control and status management
Optional 8-bit register interface via built-in LatticeSC System BusSupports the data link layer of the OBSAI RP3 specification"