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What is your preferred platform for FPGA Design Flow ?:

CORDIC

IP Vendor: 
Xilinx
IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
DSP - Digital Signal Processing
IP Supported FPGA Device: 
Spartan-3
Spartan-3E
Spartan-II
Spartan-IIE
Virtex
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-E
Virtex-II
Virtex-II Pro
IP Description: 

"The CORDIC IP core implements a generalized ""Coordinate Rotational Digital Computer (CORDIC) Algorithm"". The core implements Rectangular, Polar Conversion, Trigonometric, Hyperbolic, and Sqare Root Equations. It is available in two architectural configurations; fully parallel configuration with single cycle data throughput at the expense of silicon area, and word serial implementation with multiple cycle throughput, occupying a small silicon area. The core has a parameterizable data width from 8 to 48 bits. It has a Coarse Rotation stage extending the range of CORDIC operation to the full 360 degrees. The CORDIC core has two formats available to express the Phase Component of data samples, ""Radians"" and ""Pi Radians"". It also has optional amplitude compensation for the CORDIC Amplitude Scale Factor. The core has three rounding modes; Truncate, Round to Positive Infinity, and Round to Pos/Neg Infinity. It is optimized for speed and area, and is a fully synchronous design using a single clock.
Included with Xilinx ISE Software

Device Family Support

Virtex-4 FX

Virtex-4 LX

Virtex-4 SX

Virtex-II Pro

Virtex-II

Virtex-E

Virtex

Spartan-3E

Spartan-3

Spartan-IIE

Spartan-II

Key Features

Supports many functional configurations: vector rotation (polar to rectangular), vector translation (rectangular to polar), Sin and Cos, Sinh and Cosh, Atan and Atanh, square root

Provides control of the internal add-sub precision and the number of add-sub iterations

Optional amplitude compensation for CORDIC algorithm's amplitude scale factor

Supports multiple output rounding modes: Truncation, Round to Pos Infinity, Round to Pos/Neg Infinity and Round to Nearest Even

Word Serial architectural configuration for small area and parallel architectural configuration for high throughput"

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