World's 1st FPGA/CPLD Portal

"Features
Implements the FIPS 46-3 standard
Input memory block is configurable with shadow memory to allow input of next block while DES operation in progress
Automatic generation of key context from key data
Key memory accessible through memory interface
Electronic Codebook (ECB) or Cipher Block Chaining (CBC) modes
General Description
The CLP-02 DES/3DES core combines both algorithms into a single block which is selectable via a mode bit. The core supports both Electronic Code Book (ECB) and Cipher Block Chaining (CBC) modes of operation. The DES context consists of a single 64 bit key and a 64 bit initialization vector (IV). The 3-DES context consists of three 64 bit keys and a 64 bit IV. The IV is only used for (3)DES when it is operating in CBC mode. The context is accessed through the control processor port on the core.

The CLP-02 has two major interfaces - the control processor interface is a slave memory bus which allows an external processor to access the internal configuration registers. The memory interface is a master memory bus which accesses the data to be encrypted or decrypted."